1) Analog IC Physical Design (Layout) Engineer

We are looking for an experienced analog IC layout engineer to work closely with design team to perform physical layout of high-performance analog and mixed-signal ASICs. Responsibilities include block-level layout and verification, top level routing, floor planning, and tape-out.

Education

  • At least BSEE or equivalent.

Requirements

  • Minimum of 2 years analog CMOS layout experience.
  • Solid understanding of design rules and verification for sub-micron CMOS processes.
  • Proficiency in block level floor planning, device matching, parasitic analysis, buss drop analysis, current density, and isolation techniques.
  • Experience with floor planning and integration of top-level designs.
  • Tape-out experience including final LVS, DRC, ERC, antenna checks, density checks, and release to fabrication.
  • Experience with Cadence design environment or similar CAD tools in Unix/Linux.
  • Effective verbal and written communication skills.
  • Self-motivated, proactive, and comfortable in a startup environment.

Plus points
 Scripting for automation of CAD flow.
Knowledge of digital/SOC CAD flows.
Experience debugging and/or writing DRC and LVS decks.
Analog circuit design experience.

email: erik@neurosky.com

2) Analog IC Design Engineer

  • We are looking for an experienced analog IC design engineer to work on the development of mixed ASICs.

Education

  • At least MSEE or equivalent.

Requirements
Minimum of 5 years analog CMOS design experience in an industrial environment, covering as many as possible of the following areas:

  • Op amps, OTAs, comparators, PGAs,
  • Crystal oscillators,
  • Voltage reference circuits (e.g. bandgap, PTAT,…),
  • Supply voltage regulators,
  • A/D and D/A converters,
  • Switched capacitor filters,
  • Continuous time filters.

Ability to derive block-level specifications from system requirements.
Experience with Cadence design environment or similar CAD tools in Unix/Linux.
Design for process spread and corner cases.
Design for test and preparation of test specifications.
Good knowledge of ESD and latch-up prevention.
Experience of laboratory characterization of analog ICs.
Experience of taking designs from concept thru to commercialisation.
Effective verbal and written communication skills.
Self-motivated, proactive, and comfortable in a startup environment.

Plus points

  • Behavioural modelling skills (Matlab, verilog, C, etc)
  • Scripting for automation of design and verification (Skill, Ocean, Perl,…)
  • Knowledge of digital/SOC CAD flows.

email: erik@neurosky.com